DC=DC_0, BFHFNMIGN=BFHFNMIGN_0, USERSETMPEND=USERSETMPEND_0, IC=IC_0, STKALIGN=STKALIGN_0, DIV_0_TRP=DIV_0_TRP_0, NONBASETHRDENA=NONBASETHRDENA_0, UNALIGN_TRP=UNALIGN_TRP_0
Configuration and Control Register
| NONBASETHRDENA | Indicates how the processor enters Thread mode 0 (NONBASETHRDENA_0): processor can enter Thread mode only when no exception is active 1 (NONBASETHRDENA_1): processor can enter Thread mode from any level under the control of an EXC_RETURN value |
| USERSETMPEND | Enables unprivileged software access to the STIR 0 (USERSETMPEND_0): disable 1 (USERSETMPEND_1): enable |
| UNALIGN_TRP | Enables unaligned access traps 0 (UNALIGN_TRP_0): do not trap unaligned halfword and word accesses 1 (UNALIGN_TRP_1): trap unaligned halfword and word accesses |
| DIV_0_TRP | Enables faulting or halting when the processor executes an SDIV or UDIV instruction with a divisor of 0 0 (DIV_0_TRP_0): do not trap divide by 0 1 (DIV_0_TRP_1): trap divide by 0 |
| BFHFNMIGN | Enables handlers with priority -1 or -2 to ignore data BusFaults caused by load and store instructions. 0 (BFHFNMIGN_0): data bus faults caused by load and store instructions cause a lock-up 1 (BFHFNMIGN_1): handlers running at priority -1 and -2 ignore data bus faults caused by load and store instructions |
| STKALIGN | Indicates stack alignment on exception entry 0 (STKALIGN_0): 4-byte aligned 1 (STKALIGN_1): 8-byte aligned |
| DC | Enables L1 data cache. 0 (DC_0): L1 data cache disabled 1 (DC_1): L1 data cache enabled |
| IC | Enables L1 instruction cache. 0 (IC_0): L1 instruction cache disabled 1 (IC_1): L1 instruction cache enabled |
| BP | Always reads-as-one. It indicates branch prediction is enabled. |